Zhifan Wei

PCIe 5.0 Opens the Way for Enterprise Storage Innovation

Mr. Wei, chief engineer of Jiangsu Huacun Electronics, specializes in PCIe Gen5 enterprise-level SSD chip architecture design. He holds 38 storage patents, participates in the formulation of a number of domestic storage standards, and understands the industry's basic technology ecology, product positioning, application scenarios, and development trends.
Mr. Wei has 23 years of working experience in the IC design industry. His technical fields include chip architecture and algorithms, high-speed Serdes/LVDS interfaces, simulation circuits and large-scale digital circuit design. He participated in more than 40 chip mass production tapeout projects, and the cumulative chip mass production shipments have exceeded 500 million.
Mr. Wei used to be the general manager of SK Hynix Taiwan R&D Center, responsible for chip development, promotion and support of storage product lines.